A couple anniversaries today
Feb. 7th, 2007 01:59 am![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png){kind=small}
pseydtonneHappy birthday to ![[livejournal.com profile]](https://www.dreamwidth.org/img/external/lj-userinfo.gif)
chaggalagirl! You're a quarter of a century now... so meow! May your plans for lo mein go swimmingly and the delivery boy be seduceable.
Today is also the second anniversary of my start at IBM. I'm celebrating by dropping one ancient computer for a slightly less ancient one.
I have this habit of turning near-dead computers into fresh things. At work I have four boxes: one is the IBM desktop they handed me on my first day (P4 HT 3.0 GHz 2 GB RAM 120 GB IDE drive), one is a Sun Blade 100 (UltraSPARC 500 MHz 512 MB RAM 20 GB IDE drive), and the other two are old Dell P3 boxes. The one I retired was a P3 866 MHz 512 MB RAM with two 36 GB SCSI drives, which I have replaced with a P4 1.3 GHz 1 GB RAM. Since the old box was running Linux (Red Hat Enterprise 4 no updates), I just pulled the Adaptec 29160 card from the old box and dropped it into the slightly faster box with its high-bandwidth SCSI drives and it all worked without a flinch.
I am aware the 1.3 GHz Pentium 4 socket 423 Willamette is the very lowest speed and quality P4 ever. It was a 180nm fab stomped by lower-speed P3 Tualatins within half a year because of the 130nm fab and the old-school branch prediction.
For any non-geeks reading this: Intel's processors take huge hunks of data, break 'em into chunks, shove each chunk into its own path for semi-parallel processing (each path known as a pipeline) and then hope they all come out at the same time -- which they don't. You may have chunk A with a lot of comparison and grab instructions while chunk B has only has instructions to wait a few clock cycles to pass (halt instructions). Thus B is ready to be enacted but A isn't and the works are held up. Pentium 3 architecture used about 10 of these pipelines while the first P4's used 20 of them. They were new, so the compilers weren't used to them yet. So the internal branch prediction (where the processor guesses which chunks will need more work and thus need to schedule around it) wasn't optimized and there wasn't much of a point to upgrading except for the faster motherboard buses.
By the way, I have wicked oversimplified something I understand loosely.metahacker is probably cringing from the spiel I just unloaded. If you can re-educate me, I would be honored.
Anyway, I wanted to see whether the bus speed (throughput) meant more than the processor efficiency. Turns out... yup so far!
I should've been in bed an hour ago. Kibo and I were figuring out the problems hounding our cable modem speeds and VoIP service. It turns out older phones cannot work with VoIP and the latest build of Transmission (a really shiny BitTorrent client he uses on his Mac) had a new feature that only works as a bug so far. That bug cost us surfing ability. Blah.
-man I should be asleep, Dante
chaggalagirl! You're a quarter of a century now... so meow! May your plans for lo mein go swimmingly and the delivery boy be seduceable.Today is also the second anniversary of my start at IBM. I'm celebrating by dropping one ancient computer for a slightly less ancient one.
I have this habit of turning near-dead computers into fresh things. At work I have four boxes: one is the IBM desktop they handed me on my first day (P4 HT 3.0 GHz 2 GB RAM 120 GB IDE drive), one is a Sun Blade 100 (UltraSPARC 500 MHz 512 MB RAM 20 GB IDE drive), and the other two are old Dell P3 boxes. The one I retired was a P3 866 MHz 512 MB RAM with two 36 GB SCSI drives, which I have replaced with a P4 1.3 GHz 1 GB RAM. Since the old box was running Linux (Red Hat Enterprise 4 no updates), I just pulled the Adaptec 29160 card from the old box and dropped it into the slightly faster box with its high-bandwidth SCSI drives and it all worked without a flinch.
I am aware the 1.3 GHz Pentium 4 socket 423 Willamette is the very lowest speed and quality P4 ever. It was a 180nm fab stomped by lower-speed P3 Tualatins within half a year because of the 130nm fab and the old-school branch prediction.
For any non-geeks reading this: Intel's processors take huge hunks of data, break 'em into chunks, shove each chunk into its own path for semi-parallel processing (each path known as a pipeline) and then hope they all come out at the same time -- which they don't. You may have chunk A with a lot of comparison and grab instructions while chunk B has only has instructions to wait a few clock cycles to pass (halt instructions). Thus B is ready to be enacted but A isn't and the works are held up. Pentium 3 architecture used about 10 of these pipelines while the first P4's used 20 of them. They were new, so the compilers weren't used to them yet. So the internal branch prediction (where the processor guesses which chunks will need more work and thus need to schedule around it) wasn't optimized and there wasn't much of a point to upgrading except for the faster motherboard buses.
By the way, I have wicked oversimplified something I understand loosely.
metahacker is probably cringing from the spiel I just unloaded. If you can re-educate me, I would be honored. Anyway, I wanted to see whether the bus speed (throughput) meant more than the processor efficiency. Turns out... yup so far!
I should've been in bed an hour ago. Kibo and I were figuring out the problems hounding our cable modem speeds and VoIP service. It turns out older phones cannot work with VoIP and the latest build of Transmission (a really shiny BitTorrent client he uses on his Mac) had a new feature that only works as a bug so far. That bug cost us surfing ability. Blah.
-man I should be asleep, Dante
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Date: 2007-02-07 03:52 pm (UTC)no subject
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